Informatics Publishing Limited

M. Santhosh ¹, B. Stephen Charles ², M. N. Giri Prasad ³

Affiliations
1 Department of Electronics and Communication Engineering, Stanley Stephen College of Engineering & Technology, Kurnool, IN
2 Stanley Stephen College of Engineering and Technology, Kurnool, IN
3 Department of Electronics and Communication Engineering, JNTUCE, JNTUA, Anantapur, IN

Abstract

Image is a two dimensional plot of intensity information. A digital image is a collection of numbers representing the intensity values. The digital image is stored primarily as a matrix (more specifically as an array of multi-dimension). Hence the processing of the image is done primarily on this representation of the image. Because this representation is a raw data of pixels and distributed along the plane non-uniformly, one cannot apply any operation more effectively. The aim of this paper is to analyze the wavelet representation of an image. In this paper, the representation of image by wavelets is presented and verified the effectiveness of the representation by performing compression on the new representation. This paper proposes a new composite design metric to analyze image compression. The first generation wavelets Haar, Daubechies, Bioorthogonal, Coiflet, Symlet and Di-Meyer are considered. The work was tested on a large number of images and the results are presented.

Keywords

Image Representation, Wavelet, Compression, SPIHT.

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C. Mohan Rao ¹, B. Stephen Charles ², M. N. Giriprasad ³

Affiliations
1 Department of Elections and Communication Engineering, NBKRIST, Vidyanagar, IN
2 SS College of Engineering and Technology, Kurnool, IN
3 Department of Elections and Communication Engineering, JNTUCE, JNTUA, Anantapur, IN

Abstract

Adaptive filtering techniques are used in a wide range of applications, including echo cancellation, adaptive equalization, adaptive noise cancellation, and adaptive beamforming, while this paper presents the application of adaptive filtering to system identification problem. System identification will help in finding the system characteristics well. System identification approximates an unknown system. System identification finds numerous applications in communications. In the system identification application, the desired signal is the output of the unknown system when excited by a broadband signal, in most cases a white-noise signal. The broadband signal is also used as input for the adaptive filter. When the output MSE is minimized, the adaptive filter represents a model for the unknown system. The earlier methods of system identification use complex numerical and statistical methods by observing the output for different inputs. The present solution to the system identification problem is by the use of so called neural networks or genetic algorithm. Correspondingly adaptive filtering technique best suites the situation. Adaptive algorithms are categorized into a number of types. In this paper a detailed classification of adaptive algorithms is presented. A number of LMS based algorithms are used in the implementation of system identification. The simulation results of these algorithms are shown in the paper.

Keywords

Ystem Identification, Adaptive Filtering, LMS.

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B. KaliVara Prasad ¹, P. Satish Kumar ², B. Stephen Charles ³, T. Madhu ⁴

Affiliations
1 Department of ECE, KL University, Guntur, Andhra Pradesh, IN
2 Department of ECE, MLR Institute of Technology, Hyderabad, Andhra Pradesh, IN
3 Department of ECE, SSCET, Kurnool, Andhra Pradesh, IN
4 Department of ECE, SIET, Narsapur, Andhra Pradesh, IN

Abstract

The re-configurability of Field Programmable Gate Arrays (FPGA) plays an important role in reducing on-chip testing hardware relative to Application Specific Integrated-Circuits (ASICs). In general, fault coverage is directly related to the number and scope of test configurations that are created. To operate effectively, the specific location of the fault should be clearly identified. The fault coverage issue has been further complicated in recent years by the introduction of FPGA devices with millions of programmable switch points. This paper aims at the fault detection and location of interconnects in an FPGA. The proposed testing scheme uses a test manager, which defines a part of the chip as pattern generator and the other half as response analyzer. The chip is reconfigured several times to cover all portions of interconnect. Testing is done in two phases, phase one involves several reconfigurations intended to detect various faults in the interconnect structure. Another phase involves extensively testing the complete interconnect structure for all possible faults namely configurable interconnection points stuck on and (or) stuck off, wire stuck-at-1, wire stuck-at-0, two adjacent wires short, and wires open etc.

Keywords

FPGA, Interconnects, CLBs, Fault Diagnosis, Failure.

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